The conventional art of designing and configuring a Motion Pictures Experts Group (MPEG) encoding and decoding system is confronted with several technical limitations and difficulties. Particularly, the task of processing a video image data based on the MPEG video standard involves many complex algorithms and requires several processing stages. Each of these algorithms consists of many computationally intensive tasks, executing all the complex encoding and decoding procedures in real time. For the purpose of generating real time video images, conventional methods of configuring a MPEG system generally require a very high performance solution. A conventional configuration usually requires a digital signal processor (DSP) or embedded processor to handle mainstream processes and may also require additional hardware assist logic circuits.
However, the conventional configurations create several technical challenges and difficulties. Implementation of a conventional configuration first requires the selection of an appropriate high performance DSP platform to support the high processing demand thus causing an increase in the production costs of such system. The processor selected based on this DSP platform then extracts and executes software programs stored in the memory that causes the size and power consumptions to increase and also degrades the processing bandwidth due to the data transfer operations between the memory and processor. The handling and control of data transfer sequencing and synchronization further adds to the overhead of DSP overhead that further slow down the MPEG encode/decode operations.
Even though current digital video encoding and compression techniques are able to take advantage of redundancies inherent in natural imagery to dramatically improve the efficiency in video image data storage and processing and to allow for faster transmission of images, there are still needs to lower the power consumption, to increase the processing speed and to achieve more compact video storage. Particularly, this is a challenging task as the decoding of the MPEG compressed video data involves five basic operations: 1) bit stream parser and variable decoder; 2) inverse scan and run-level code decoder; 3) de-quantization and inverse discrete cosine transform function (IDCT); 4) motion compensation; and 5) YUV to RGB color conversion.
For example, FIG. 1 shows a functional block diagram of a conventional MPEG video image display system, in accordance with the prior art. In particular, DSP/RISC 110 controls, manages and co-processes the fixed functions necessary for the image data processing, such as discrete cosine transform function (DCT), motion estimation (ME) and motion compensation), and any components of codec functions. These functions include the five operations described above. A quantitative estimate of the complexity of the general MPEG video real-time decoding process in terms of the number of required instruction cycles per second reveals that, for a typical general-purpose RISC processor, all of the resources of the microprocessor are exhausted by, for example, the color conversion operation alone. Real-time decoding refers to decoding at the rate at which the video signals were originally recorded (e.g., 30 frames per second). An exemplary digital television signal generates about 10.4 million picture elements (pixels) per second. Since each pixel has three independent color components (primary colors: red, green and blue), the total data element rate is more than 30 million per second, which is of the same order of magnitude as current CPU clock speeds. Thus, even at the highest current CPU clock speed of 200 MHz, there are only 20 clock cycles available for processing each pixel, and less than 7 clocks per color component.
Furthermore, to convert the video signals of a digital television signal from YUV format to RGB format in real time, for example, using even the fastest conventional microprocessors requires approximately 200 million instruction cycles per second (nearly all of the data processing bandwidth of such a microprocessor). Depending on the type of processor used and several other factors such as bit rate, average symbol rate, etc., implementing each of the IDCT function and motion compensation in real time may require, for example, anywhere from approximately 90 million operations per second (MOPS) to 200 MOPS for full resolution images. Existing general-purpose microprocessors are extremely inefficient in handling real-time decompression of full-size, digital motion video signals compressed according to MPEG standards. Typically, additional hardware is needed for such real-time decompression, which adds to system complexity and cost.
The requirement for performing these tasks using a processor that involves the execution of software programs increase the costs, power consumption, and size of the system and further degrades the bandwidth and speed of video image data processing. For these reasons, there is a need for a more efficient implementation of real-time decompression of digital motion video compressed according to MPEG standards such that the difficulties and limitations of the conventional techniques can be resolved.